In integrated circuits, a “clock skew” is a phenomenon which at least two clock signals, which may originate from, e.g., the same clock generation circuits arrives at different times.
Typically, as exemplary shown in FIG. 1, the clock skew adjustment within integrated circuits is performed with a simple skew sensor 20 which detects which one of two input clock signals Clk1′ and Clk2′ is later in time than or earlier than another. An algorithm for the clock skew control is to minimize the clock skew by delaying a fast clock signal of the two clock signals Clk1′ and Clk2′ or accelerating a slow clock signal thereof.
Referring to FIG. 1, the clock skew adjustment system 1 may receive clock signals Clk1′_in and Clk2′_in, delay the same through the delay units 30-1 and 30-2, respectively, by the delays of (D+ΔtA) and (D+ΔtB) for the clock skew adjustment, and output clock signals Clk1′ and Clk2′, between which clock skew has been adjusted, through nodes N1 and N2, respectively. The delayed output clock signals Clk1′ and Clk2′ are input to the skew sensor 20, and the skew sensor 20 may output a signal, as shown in Table 1 below, depending on a difference ΔT in arrival time between the two clock signals Clk1′ and Clk2′.
ΔTSensor OutputΔT < −SL0−S ≤ ΔT < SUndeterministic state between L0 and L1ΔT ≥ SL1
Here, ‘S’ denotes a sensor resolution (e.g., a threshold of differences of the arrival times of the clocks). When the clock skew ΔT is such that ΔT<−S, and ΔT≥S, the skew sensor 20 may output logic 0 L0 (e.g., logic low) and logic 1 L1 (e.g., logic high), respectively. However, when the clock skew ΔT is such that −S≤ΔT<S, which will be referred to as an “uncertainty region”, the skew sensor 20 might not decide which one of the clock signals Clk1′ and Clk2′ is earlier than the other, outputting either of the logic 1 L1 or the logic 0 L0 in a random manner.
If the minimal step size of each delay unit 30-1 and 30-2 is larger than the uncertainty region of the skew sensor 20, the clock skew adjustment system 1 might not enter a steady state, jumping back and forth between two consecutive delay settings, and thus, jitters may occur on the clock signals.
Thus, there is a need for a clock skew adjustment technique to reduce jitter on clock signals while maintaining long-term stability.